1. Field of Invention
Example embodiments of the present invention relate to the field of semiconductor manufacturing. More particularly, example embodiments of the present invention relate to methods of fabricating wafer-level stack packages, in which semiconductor chips are stacked at a wafer level and connected to one another using a conductive through via.
2. Description of the Related Art
Recently, a wafer-level three-dimensional (3D) chip stack package has received much attention in the semiconductor industry due to its advantages such as high performance, short vertical interconnections, high density, multi-functionality, and/or small dimensions. In the wafer-level 3D chip stack package, typically a conductive through via is formed to vertically extend through individual wafers and chips in the wafers are subsequently singulated and stacked to be electrically connected to one another using conductive through vias to form a wafer stack package (WSP). Conventionally, the conductive through via is formed after a passivation layer is formed over the wafers, as will be described below.
FIG. 1 is a flow chart describing a conventional method of forming a WSP discussed above. At step S10, integrated circuits are formed on a wafer using conventional chip fabrication processes. This process includes the formation of discrete devices such as a transistor and a resistor, the formation of a final metal layer to interconnect discrete devices to form integrated circuits. Lastly, a passivation layer is formed to protect the chips formed on the wafer.
In the next step at S20, an electrical die sort (EDS) test is performed on the wafer. Thereafter, at step S30, a conductive through via is formed into the wafer having the passivation layer. Then, a plurality of semiconductor chips with the conductive through via from the wafer are stacked to form a WSP using a redistribution layer process. If a defect occurring at step S30 is not detected until the EDS test performed after the stacking of the chips, all of semiconductor chips in the stack must be scrapped. Consequently, to avoid these risks, 2nd or additional EDS test may need to be performed repeatedly after forming the conductive through via. See step S40.
However, these processing steps described above are time consuming and substantially increase manufacturing costs.